Network Working Group I. Widjaja
Request For Comments: 2682 Fujitsu Network Communications
Category: Informational A. Elwalid
Bell Labs, Lucent Technologies
September 1999
Network Working Group I. Widjaja
Request For Comments: 2682 Fujitsu Network Communications
Category: Informational A. Elwalid
Bell Labs, Lucent Technologies
September 1999
Performance Issues in VC-Merge Capable ATM LSRs
支持VC合并的ATM LSR中的性能问题
Status of this Memo
本备忘录的状况
This memo provides information for the Internet community. It does not specify an Internet standard of any kind. Distribution of this memo is unlimited.
本备忘录为互联网社区提供信息。它没有规定任何类型的互联网标准。本备忘录的分发不受限制。
Copyright Notice
版权公告
Copyright (C) The Internet Society (1999). All Rights Reserved.
版权所有（C）互联网协会（1999年）。版权所有。
Abstract
摘要
VC merging allows many routes to be mapped to the same VC label, thereby providing a scalable mapping method that can support thousands of edge routers. VC merging requires reassembly buffers so that cells belonging to different packets intended for the same destination do not interleave with each other. This document investigates the impact of VC merging on the additional buffer required for the reassembly buffers and other buffers. The main result indicates that VC merging incurs a minimal overhead compared to non-VC merging in terms of additional buffering. Moreover, the overhead decreases as utilization increases, or as the traffic becomes more bursty.
VC合并允许将多条路由映射到同一个VC标签，从而提供一种可扩展的映射方法，可支持数千个边缘路由器。VC合并需要重新组合缓冲区，以便属于同一目的地的不同数据包的单元不会相互交织。本文件研究了VC合并对重新组装缓冲区和其他缓冲区所需的额外缓冲区的影响。主要结果表明，就附加缓冲而言，与非VC合并相比，VC合并产生的开销最小。此外，开销随着利用率的增加而减少，或者随着流量变得更加突发而减少。
Recently some radical proposals to overhaul the legacy router architectures have been presented by several organizations, notably the Ipsilon's IP switching [1], Cisco's Tag switching [2], Toshiba's CSR [3], IBM's ARIS [4], and IETF's MPLS [5]. Although the details of their implementations vary, there is one fundamental concept that is shared by all these proposals: map the route information to short fixed-length labels so that next-hop routers can be determined by direct indexing.
最近，一些组织提出了一些彻底改革传统路由器体系结构的激进建议，特别是Ipsilon的IP交换[1]、Cisco的标签交换[2]、东芝的CSR[3]、IBM的ARIS[4]和IETF的MPLS[5]。尽管它们的实现细节各不相同，但所有这些方案都有一个基本概念：将路由信息映射到固定长度的短标签，以便通过直接索引确定下一跳路由器。
Although any layer 2 switching mechanism can in principle be applied, the use of ATM switches in the backbone network is believed to be a very attractive solution since ATM hardware switches have been extensively studied and are widely available in many different
尽管原则上可以应用任何第2层交换机制，但在主干网中使用ATM交换机被认为是一个非常有吸引力的解决方案，因为ATM硬件交换机已经得到了广泛的研究，并且在许多不同的网络中都广泛可用
architectures. In this document, we will assume that layer 2 switching uses ATM technology. In this case, each IP packet may be segmented to multiple 53-byte cells before being switched. Traditionally, AAL 5 has been used as the encapsulation method in data communications since it is simple, efficient, and has a powerful error detection mechanism. For the ATM switch to forward incoming cells to the correct outputs, the IP route information needs to be mapped to ATM labels which are kept in the VPI or/and VCI fields. The relevant route information that is stored semi-permanently in the IP routing table contains the tuple (destination, next-hop router). The route information changes when the network state changes and this typically occurs slowly, except during transient cases. The word "destination" typically refers to the destination network (or CIDR prefix), but can be readily generalized to (destination network, QoS), (destination host, QoS), or many other granularities. In this document, the destination can mean any of the above or other possible granularities.
架构。在本文中，我们假设第2层交换使用ATM技术。在这种情况下，每个IP分组在被切换之前可以被分割成多个53字节的单元。传统上，AAL 5被用作数据通信中的封装方法，因为它简单、高效，并且具有强大的错误检测机制。为了使ATM交换机将传入信元转发到正确的输出，IP路由信息需要映射到保存在VPI或/和VCI字段中的ATM标签。IP路由表中半永久性存储的相关路由信息包含元组（目的地，下一跳路由器）。当网络状态发生变化时，路由信息会发生变化，这通常会缓慢发生，但在瞬态情况下除外。“目的地”一词通常指目的地网络（或CIDR前缀），但可以容易地概括为（目的地网络，QoS）、（目的地主机，QoS）或许多其他粒度。在本文档中，目的地可以指上述任何一种或其他可能的粒度。
Several methods of mapping the route information to ATM labels exist. In the simplest form, each source-destination pair is mapped to a unique VC value at a switch. This method, called the non-VC merging case, allows the receiver to easily reassemble cells into respective packets since the VC values can be used to distinguish the senders. However, if there are n sources and destinations, each switch is potentially required to manage O(n^2) VC labels for full-meshed connectivity. For example, if there are 1,000 sources/destinations, then the size of the VC routing table is on the order of 1,000,000 entries. Clearly, this method is not scalable to large networks. In the second method called VP merging, the VP labels of cells that are intended for the same destination would be translated to the same outgoing VP value, thereby reducing VP consumption downstream. For each VP, the VC value is used to identify the sender so that the receiver can reconstruct packets even though cells from different packets are allowed to interleave. Each switch is now required to manage O(n) VP labels - a considerable saving from O(n^2). Although the number of label entries is considerably reduced, VP merging is limited to only 4,096 entries at the network-to-network interface. Moreover, VP merging requires coordination of the VC values for a given VP, which introduces more complexity. A third method, called VC merging, maps incoming VC labels for the same destination to the same outgoing VC label. This method is scalable and does not have the space constraint problem as in VP merging. With VC merging, cells for the same destination is indistinguishable at the output of a switch. Therefore, cells belonging to different packets for the same destination cannot interleave with each other, or else the receiver will not be able to reassemble the packets. With VC merging, the boundary between two adjacent packets are identified by the "End-of-Packet" (EOP) marker used by AAL 5.
存在几种将路由信息映射到ATM标签的方法。在最简单的形式中，每个源-目标对都映射到交换机上的唯一VC值。这种方法称为非VC合并案例，它允许接收方轻松地将单元格重新组合到各自的数据包中，因为VC值可用于区分发送方。但是，如果有n个源和目标，则可能需要每个交换机管理O（n^2）个VC标签以实现完全网状连接。例如，如果有1000个源/目的地，则VC路由表的大小大约为1000000个条目。显然，这种方法无法扩展到大型网络。在第二种称为VP合并的方法中，用于相同目的地的单元的VP标签将被转换为相同的输出VP值，从而减少下游VP消耗。对于每个VP，VC值用于标识发送方，以便接收方可以重建数据包，即使来自不同数据包的单元被允许交错。现在需要每个交换机来管理O（n）VP标签，这比O（n^2）节省了很多。虽然标签条目的数量大大减少，但VP合并仅限于网络到网络接口处的4096个条目。此外，VP合并需要协调给定VP的VC值，这会带来更大的复杂性。第三种方法称为VC合并，将同一目标的传入VC标签映射到同一传出VC标签。该方法具有可扩展性，不存在VP合并中的空间约束问题。通过VC合并，同一目的地的单元格在交换机的输出端无法区分。因此，属于同一目的地的不同分组的小区不能相互交织，否则接收机将无法重新组合分组。通过VC合并，两个相邻数据包之间的边界由AAL 5使用的“数据包结束”（EOP）标记标识。
It is worthy to mention that cell interleaving may be allowed if we use the AAL 3/4 Message Identifier (MID) field to identify the sender uniquely. However, this method has some serious drawbacks as: 1) the MID size may not be sufficient to identify all senders, 2) the encapsulation method is not efficient, 3) the CRC capability is not as powerful as in AAL 5, and 4) AAL 3/4 is not as widely supported as AAL 5 in data communications.
值得一提的是，如果我们使用AAL 3/4消息标识符（MID）字段来唯一标识发送方，则可以允许小区交错。然而，这种方法有一些严重的缺点：1）中等大小可能不足以识别所有发送方，2）封装方法效率不高，3）CRC功能不如AAL 5强大，4）AAL 3/4在数据通信中没有AAL 5广泛支持。
Before VC merging with no cell interleaving can be qualified as the most promising approach, two main issues need to be addressed. First, the feasibility of an ATM switch that is capable of merging VCs needs to be investigated. Second, there is widespread concern that the additional amount of buffering required to implement VC merging is excessive and thus making the VC-merging method impractical. Through analysis and simulation, we will dispel these concerns in this document by showing that the additional buffer requirement for VC merging is minimal for most practical purposes. Other performance related issues such as additional delay due to VC merging will also be discussed.
在无单元交织的VC合并成为最有前途的方法之前，需要解决两个主要问题。首先，需要研究能够合并VCs的ATM交换机的可行性。其次，人们普遍担心，实现VC合并所需的额外缓冲量过多，从而使VC合并方法不切实际。通过分析和模拟，我们将在本文中消除这些顾虑，说明VC合并所需的额外缓冲区对于大多数实际目的来说是最小的。还将讨论其他与性能相关的问题，如VC合并导致的额外延迟。
In principle, the reassembly buffers can be placed at the input or output side of a switch. If they are located at the input, then the switch fabric has to transfer all cells belonging to a given packet in an atomic manner since cells are not allowed to interleave. This requires the fabric to perform frame switching which is not flexible nor desirable when multiple QoSs need to be supported. On the other hand, if the reassembly buffers are located at the output, the switch fabric can forward each cell independently as in normal ATM switching. Placing the reassembly buffers at the output makes an output-buffered ATM switch a natural choice.
原则上，重新组装缓冲器可放置在开关的输入或输出侧。如果它们位于输入端，则交换结构必须以原子方式传输属于给定分组的所有小区，因为小区不允许交织。这要求结构执行帧切换，这在需要支持多个qos时既不灵活也不可取。另一方面，如果重组缓冲器位于输出端，则交换结构可以像在正常ATM交换中一样独立地转发每个信元。在输出端放置重新组装的缓冲器使输出缓冲ATM交换机成为一种自然选择。
We consider a generic output-buffered VC-merge capable MPLS switch with VCI translation performed at the output. Other possible architectures may also be adopted. The switch consists of a non-blocking cell switch fabric and multiple output modules (OMs), each is associated with an output port. Each arriving ATM cell is appended with two fields containing an output port number and an input port number. Based on the output port number, the switch fabric forwards each cell to the correct output port, just as in normal ATM switches. If VC merging is not implemented, then the OM consists of an output buffer. If VC merging is implemented, the OM contains a number of reassembly buffers (RBs), followed by a merging unit, and an output buffer. Each RB typically corresponds to an incoming VC value. It is important to note that each buffer is a logical buffer, and it is envisioned that there is a common pool of memory for the reassembly buffers and the output buffer.
我们考虑一个通用的输出缓冲的VC合并的MPLS交换机，在输出端执行VCI转换。也可以采用其他可能的架构。交换机由非阻塞单元交换机结构和多个输出模块（OMs）组成，每个模块与一个输出端口相关联。每个到达的ATM信元都附加了两个字段，其中包含一个输出端口号和一个输入端口号。根据输出端口号，交换机结构将每个信元转发到正确的输出端口，就像在普通ATM交换机中一样。如果未实现VC合并，则OM由输出缓冲区组成。如果实现了VC合并，OM包含许多重组缓冲区（RB），后面是合并单元和输出缓冲区。每个RB通常对应于传入的VC值。需要注意的是，每个缓冲区都是一个逻辑缓冲区，可以设想，重组缓冲区和输出缓冲区有一个公共内存池。
The purpose of the RB is to ensure that cells for a given packet do not interleave with other cells that are merged to the same VC. This mechanism (called store-and-forward at the packet level) can be accomplished by storing each incoming cell for a given packet at the RB until the last cell of the packet arrives. When the last cell arrives, all cells in the packet are transferred in an atomic manner to the output buffer for transmission to the next hop. It is worth pointing out that performing a cut-through mode at the RB is not recommended since it would result in wastage of bandwidth if the subsequent cells are delayed. During the transfer of a packet to the output buffer, the incoming VCI is translated to the outgoing VCI by the merging unit. To save VC translation table space, different incoming VCIs are merged to the same outgoing VCI during the translation process if the cells are intended for the same destination. If all traffic is best-effort, full-merging where all incoming VCs destined for the same destination network are mapped to the same outgoing VC, can be implemented. However, if the traffic is composed of multiple classes, it is desirable to implement partial merging, where incoming VCs destined for the same (destination network, QoS) are mapped to the same outgoing VC.
RB的目的是确保给定数据包的小区不会与合并到同一VC的其他小区交织。这种机制（在包级别称为存储和转发）可以通过将给定包的每个传入单元存储在RB上直到包的最后一个单元到达来实现。当最后一个小区到达时，数据包中的所有小区都以原子方式传输到输出缓冲区，以便传输到下一跳。值得指出的是，不建议在RB处执行直通模式，因为如果后续小区延迟，则会导致带宽浪费。在将数据包传输到输出缓冲区的过程中，合并单元将传入VCI转换为传出VCI。为了节省VC转换表空间，如果单元格用于同一目的地，则在转换过程中，不同的传入VCI将合并到相同的传出VCI。如果所有流量都尽最大努力，则可以实现完全合并，其中所有目的地为同一目的地网络的传入VC映射到同一传出VC。然而，如果业务由多个类组成，则需要实现部分合并，其中目的地为相同（目的地网络，QoS）的传入VC映射到相同的传出VC。
Regardless of whether full merging or partial merging is implemented, the output buffer may consist of a single FIFO buffer or multiple buffers each corresponding to a destination network or (destination network, QoS). If a single output buffer is used, then the switch essentially tries to emulate frame switching. If multiple output buffers are used, VC merging is different from frame switching since cells of a given packet are not bound to be transmitted back-to-back. In fact, fair queueing can be implemented so that cells from their respective output buffers are served according to some QoS requirements. Note that cell-by-cell scheduling can be implemented with VC merging, whereas only packet-by-packet scheduling can be implemented with frame switching. In summary, VC merging is more flexible than frame switching and supports better QoS control.
无论是实现完全合并还是部分合并，输出缓冲区可能由单个FIFO缓冲区或多个缓冲区组成，每个缓冲区对应于目标网络或（目标网络，QoS）。如果使用单个输出缓冲区，则交换机基本上尝试模拟帧切换。如果使用多个输出缓冲区，VC合并不同于帧交换，因为给定数据包的单元不一定要背靠背传输。事实上，可以实现公平排队，以便根据某些QoS要求为来自各自输出缓冲区的小区提供服务。注意，可以通过VC合并实现逐单元调度，而只有逐包调度可以通过帧交换实现。总之，VC合并比帧交换更灵活，支持更好的QoS控制。
This section compares the VC-merging switch and the non-VC merging switch. The non-VC merging switch is analogous to the traditional output-buffered ATM switch, whereby cells of any packets are allowed to interleave. Since each cell is a distinct unit of information, the non-VC merging switch is a work-conserving system at the cell level. On the other hand, the VC-merging switch is non-work conserving so its performance is always lower than that of the non-VC merging switch. The main objective here is to study the effect of VC merging on performance implications of MPLS switches such as additional delay, additional buffer, etc., subject to different traffic conditions.
本节比较VC合并开关和非VC合并开关。非VC合并交换机类似于传统的输出缓冲ATM交换机，允许任何数据包的信元进行交织。由于每个单元都是不同的信息单元，因此非VC合并开关在单元级别上是一个节省工作的系统。另一方面，VC合并开关是非工作节约型的，因此其性能总是低于非VC合并开关。本文的主要目的是研究VC合并对MPLS交换机性能的影响，例如，在不同的流量条件下，额外的延迟、额外的缓冲区等。
In the simulation, the arrival process to each reassembly buffer is an independent ON-OFF process. Cells within an ON period form a single packet. During an OFF periof, the slots are idle. Note that the ON-OFF process is a general process that can model any traffic process.
在仿真中，每个重组缓冲器的到达过程是一个独立的开关过程。一个接通周期内的单元形成一个数据包。在关闭期间，插槽处于空闲状态。请注意，ON-OFF流程是一个通用流程，可以对任何流量流程进行建模。
We first investigate the effect of switch utilization on the additional buffer requirement for a given overflow probability. To carry the comparison, we analyze the VC-merging and non-VC merging case when the average packet size is equal to 10 cells, using geometrically distributed packet sizes and packet interarrival times, with cells of a packet arriving contiguously (later, we consider other distributions). The results show, as expected, the VC-merging switch requires more buffers than the non-VC merging switch. When the utilization is low, there may be relatively many incomplete packets in the reassembly buffers at any given time, thus wasting storage resource. For example, when the utilization is 0.3, VC merging requires an additional storage of about 45 cells to achieve the same overflow probability. However, as the utilization increases to 0.9, the additional storage to achieve the same overflow probability drops to about 30 cells. The reason is that when traffic intensity increases, the VC-merging system becomes more work-conserving.
我们首先研究在给定溢出概率下，交换机利用率对额外缓冲区需求的影响。为了进行比较，我们分析了VC合并和非VC合并的情况下，当平均分组大小等于10个小区时，使用几何分布的分组大小和分组到达时间，连续到达的分组的小区（稍后，我们考虑其他分布）。结果表明，正如预期的那样，VC合并开关比非VC合并开关需要更多的缓冲区。当利用率较低时，在任何给定时间，重组缓冲区中可能存在相对较多的不完整数据包，从而浪费存储资源。例如，当利用率为0.3时，VC合并需要额外存储约45个单元，以实现相同的溢出概率。然而，随着利用率增加到0.9，实现相同溢出概率的额外存储将下降到大约30个单元。原因是当交通强度增加时，VC合并系统变得更加节省工作。
It is important to note that ATM switches must be dimensioned at high utilization value (in the range of 0.8-0.9) to withstand harsh traffic conditions. At the utilization of 0.9, a VC-merge ATM switch requires a buffer of size 976 cells to provide an overflow probability of 10^{-5}, whereas an non-VC merge ATM switch requires a buffer of size 946. These numbers translate the additional buffer requirement for VC merging to about 3% - hardly an additional buffering cost.
需要注意的是，ATM交换机的尺寸必须为高利用率（在0.8-0.9范围内），以承受恶劣的业务条件。在利用率为0.9时，VC合并ATM交换机需要大小为976个信元的缓冲区，以提供10^{-5}的溢出概率，而非VC合并ATM交换机需要大小为946的缓冲区。这些数字将VC合并所需的额外缓冲区转换为3%左右，几乎不需要额外的缓冲成本。
We now vary the average packet size to see the impact on the buffer requirement. We fix the utilization to 0.5 and use two different average packet sizes; that is, B=10 and B=30. To achieve the same overflow probability, VC merging requires an additional buffer of about 40 cells (or 4 packets) compared to non-VC merging when B=10. When B=30, the additional buffer requirement is about 90 cells (or 3 packets). As expected, the additional buffer requirement in terms of cells increases as the packet size increases. However, the additional buffer requirement is roughly constant in terms of packets.
现在，我们改变平均数据包大小以查看对缓冲区需求的影响。我们将利用率固定为0.5，并使用两种不同的平均数据包大小；也就是说，B=10和B=30。为了达到相同的溢出概率，与B=10时的非VC合并相比，VC合并需要大约40个单元（或4个数据包）的额外缓冲区。当B=30时，额外的缓冲区需求约为90个单元（或3个数据包）。正如预期的那样，随着数据包大小的增加，对小区的额外缓冲区需求也会增加。然而，对于数据包来说，额外的缓冲区需求大致不变。
There may be some concern that VC merging may require too much buffering when the number of reassembly buffers increases, which would happen if the switch size is increased or if cells for packets going to different destinations are allowed to interleave. We will show that the concern is unfounded since buffer sharing becomes more efficient as the number of reassembly buffers increases.
可能有人担心，当重新组装缓冲区的数量增加时，VC合并可能需要太多的缓冲，如果交换机大小增加，或者如果允许前往不同目的地的数据包的单元交错，就会发生这种情况。我们将证明这种担心是没有根据的，因为随着重组缓冲区数量的增加，缓冲区共享变得更加有效。
To demonstrate our argument, we consider the overflow probability for VC merging for several values of reassembly buffers (N); i.e., N=4, 8, 16, 32, 64, and 128. The utilization is fixed to 0.8 for each case, and the average packet size is chosen to be 10. For a given overflow probability, the increase in buffer requirement becomes less pronounced as N increases. Beyond a certain value (N=32), the increase in buffer requirement becomes insignificant. The reason is that as N increases, the traffic gets thinned and eventually approaches a limiting process.
为了证明我们的论点，我们考虑了VC合并的几个概率的重组缓冲区（N）的溢出概率；i、 例如，N=4、8、16、32、64和128。对于每种情况，利用率固定为0.8，平均分组大小选择为10。对于给定的溢出概率，随着N的增加，缓冲区需求的增加变得不那么明显。超过某个值（N=32），缓冲区需求的增加变得微不足道。原因是，随着N的增加，流量变少，最终接近极限过程。
We now turn our attention to different traffic processes. First, we use the same ON period distribution and change the OFF period distribution from geometric to hypergeometric which has a larger Square Coefficient of Variation (SCV), defined to be the ratio of the variance to the square of the mean. Here we fix the utilization at 0.5. As expected, the switch performance degrades as the SCV increases in both the VC-merging and non-VC merging cases. To achieve a buffer overflow probability of 10^{-4}, the additional buffer required is about 40 cells when SCV=1, 26 cells when SCV=1.5, and 24 cells when SCV=2.6. The result shows that VC merging becomes more work-conserving as SCV increases. In summary, as the interarrival time between packets becomes more bursty, the additional buffer requirement for VC merging diminishes.
我们现在将注意力转向不同的交通流程。首先，我们使用相同的周期分布，并将非周期分布从几何改为超几何，超几何具有较大的平方变异系数（SCV），定义为方差与平均值平方的比率。这里我们将利用率固定为0.5。正如预期的那样，在VC合并和非VC合并情况下，交换机性能会随着SCV的增加而降低。为了实现10^{-4}的缓冲区溢出概率，当SCV=1时，所需的额外缓冲区约为40个单元，当SCV=1.5时为26个单元，当SCV=2.6时为24个单元。结果表明，随着SCV的增加，VC合并变得更加节省工作量。总之，随着数据包之间的到达间隔时间变得更加突发，VC合并所需的额外缓冲区减少。
Up to now, the packet size has been modeled as a geometric distribution with a certain parameter. We modify the packet size distribution to a more realistic one for the rest of this document. Since the initial deployment of VC-merge capable ATM switches is likely to be in the core network, it is more realistic to consider the packet size distribution in the Wide Area Network. To this end, we refer to the data given in [6]. The data collected on Feb 10, 1996, in FIX-West network, is in the form of probability mass function versus packet size in bytes. Data collected at other dates closely resemble this one.
到目前为止，数据包大小已被建模为具有一定参数的几何分布。在本文档的其余部分中，我们将数据包大小分布修改为更现实的分布。由于VC可合并ATM交换机的初始部署很可能在核心网中，所以考虑广域网中的分组大小分布更为现实。为此，我们参考了[6]中给出的数据。1996年2月10日在FIX West网络中收集的数据以概率质量函数的形式表示，数据包大小以字节为单位。在其他日期收集的数据与此非常相似。
The distribution appears bi-modal with two big masses at 40 bytes (about a third) due to TCP acknowledgment packets, and 552 bytes (about 22 percent) due to Maximum Transmission Unit (MTU) limitations in many routers. Other prominent packet sizes include 72 bytes (about 4.1 percent), 576 bytes (about 3.6 percent), 44 bytes (about 3 percent), 185 bytes (about 2.7 percent), and 1500 bytes (about 1.5 percent) due to Ethernet MTU. The mean packet size is 257 bytes, and the variance is 84,287 bytes^2. Thus, the SCV for the Internet packet size is about 1.1.
由于TCP确认数据包的原因，该分布呈现双模分布，两个大的质量分别为40字节（约三分之一）和552字节（约22%），这是由于许多路由器中的最大传输单元（MTU）限制。由于以太网MTU，其他主要的数据包大小包括72字节（约4.1%）、576字节（约3.6%）、44字节（约3%）、185字节（约2.7%）和1500字节（约1.5%）。平均数据包大小为257字节，方差为84287字节^2。因此，因特网分组大小的SCV约为1.1。
To convert the IP packet size in bytes to ATM cells, we assume AAL 5 using null encapsulation where the additional overhead in AAL 5 is 8 bytes long [7]. Using the null encapsulation technique, the average packet size is about 6.2 ATM cells.
为了将以字节为单位的IP数据包大小转换为ATM信元，我们假设AAL 5使用空封装，其中AAL 5中的额外开销为8字节长[7]。使用空封装技术，平均数据包大小约为6.2个ATM信元。
We examine the buffer overflow probability against the buffer size using the Internet packet size distribution. The OFF period is assumed to have a geometric distribution. Again, we find that the same behavior as before, except that the buffer requirement drops with Internet packets due to smaller average packet size.
我们使用Internet数据包大小分布检查缓冲区溢出概率与缓冲区大小的关系。假设关闭周期具有几何分布。同样，我们发现与以前相同的行为，只是由于平均数据包大小较小，互联网数据包的缓冲区需求下降。
3.6 Effect of Correlated Interarrival Times on Additional Buffer Requirement
3.6 相关到达间隔时间对额外缓冲需求的影响
To model correlated interarrival times, we use the DAR(p) process (discrete autoregressive process of order p) [8], which has been used to accurately model video traffic (Star Wars movie) in [9]. The DAR(p) process is a p-th order (lag-p) discrete-time Markov chain. The state of the process at time n depends explicitly on the states at times (n-1), ..., (n-p).
为了对相关的到达间隔时间进行建模，我们使用了DAR（p）过程（p阶离散自回归过程）[8]，该过程在[9]中已被用于准确地建模视频流量（星球大战电影）。DAR（p）过程是一个p阶（lag-p）离散时间马尔可夫链。过程在时间n的状态明确地取决于时间（n-1），…，（n-p）的状态。
We examine the overflow probability for the case where the interarrival time between packets is geometric and independent, and the case where the interarrival time is geometric and correlated to the previous one with coefficient of correlation equal to 0.9. The empirical distribution of the Internet packet size from the last section is used. The utilization is fixed to 0.5 in each case. Although, the overflow probability increases as p increases, the additional amount of buffering actually decreases for VC merging as p, or equivalently the correlation, increases. One can easily conclude that higher-order correlation or long-range dependence, which occurs in self-similar traffic, will result in similar qualitative performance.
我们检验了数据包之间的间隔时间是几何的且独立的情况下的溢出概率，以及间隔时间是几何的且与前一个数据包相关且相关系数等于0.9的情况下的溢出概率。使用上一节中互联网数据包大小的经验分布。在每种情况下，利用率固定为0.5。虽然溢出概率随着p的增加而增加，但VC合并的额外缓冲量实际上随着p的增加而减少，或者等效地，相关性增加。我们很容易得出结论，自相似业务中出现的高阶相关性或长程相关性将导致类似的定性性能。
The discussions up to now have assumed that cells within a packet arrive back-to-back. When traffic shaping is implemented, adjacent cells within the same packet would typically be spaced by idle slots. We call such sources as "slow sources". Adjacent cells within the same packet may also be perturbed and spaced as these cells travel downstream due to the merging and splitting of cells at preceding nodes.
到目前为止的讨论都假设数据包中的单元是背靠背到达的。当实现业务整形时，同一分组内的相邻小区通常由空闲时隙隔开。我们称之为“慢源”。由于前面节点上的小区合并和分裂，当这些小区向下游移动时，同一分组内的相邻小区也可能受到干扰并被隔开。
Here, we assume that each source transmits at the rate of r_s (0 < r_s < 1), in units of link speed, to the ATM switch. To capture the merging and splitting of cells as they travel in the network, we will also assume that the cell interarrival time within a packet is ran-domly perturbed. To model this perturbation, we stretch the original ON period by 1/r_s, and flip a Bernoulli coin with parameter r_s during the stretched ON period. In other words, a slot would contain a cell with probability r_s, and would be idle with probability 1-r_s during the ON period. By doing so, the average packet size remains the same as r_s is varied. We simulated slow sources on the VC-merge ATM switch using the Internet packet size distribution with r_s=1 and r_s=0.2. The packet interarrival time is assumed to be geometrically distributed. Reducing the source rate in general reduces the stresses on the ATM switches since the traffic becomes smoother. With VC merging, slow sources also have the effect of increasing the reassembly time. At utilization of 0.5, the reassembly time is more dominant and causes the slow source (with r_s=0.2) to require more buffering than the fast source (with r_s=1). At utilization of 0.8, the smoother traffic is more dominant and causes the slow source (with r_s=0.2) to require less buffering than the fast source (with r_s=1). This result again has practical consequences in ATM switch design where buffer dimensioning is performed at reasonably high utilization. In this situation, slow sources only help.
这里，我们假设每个信源以链路速度为单位，以r_s（0<r_s<1）的速率向ATM交换机传输数据。为了捕获在网络中移动的小区的合并和分裂，我们还将假设数据包中的小区到达间隔时间受到扰动。为了模拟这种扰动，我们将原始的ON周期拉伸1/r_s，并在拉伸的ON周期内投掷一枚带有参数r_s的伯努利硬币。换句话说，时隙将包含一个概率为r_s的单元，并且在接通期间将以概率1-r_s空闲。通过这样做，平均分组大小保持不变，因为rs是变化的。我们使用r_s=1和r_s=0.2的Internet数据包大小分布模拟了VC merge ATM交换机上的慢源。假设包的到达间隔时间是几何分布的。降低信源速率通常会降低ATM交换机上的压力，因为通信变得更加平滑。使用VC合并，慢源也会增加重新组装时间。在利用率为0.5时，重新组装时间占主导地位，导致慢源（r_s=0.2）比快源（r_s=1）需要更多的缓冲。在利用率为0.8时，更平滑的流量占主导地位，并导致慢源（r_s=0.2）比快源（r_s=1）需要更少的缓冲。这一结果在ATM交换机设计中同样具有实际意义，在ATM交换机设计中，缓冲区尺寸的确定是在合理的高利用率下进行的。在这种情况下，缓慢的资源只能起到帮助作用。
It is of interest to see the impact of cell reassembly on packet delay. Here we consider the delay at one node only; end-to-end delays are subject of ongoing work. We define the delay of a packet as the time between the arrival of the first cell of a packet at the switch and the departure of the last cell of the same packet. We study the average packet delay as a function of utilization for both VC-merging and non-VC merging switches for the case r_s=1 (back-to-back cells in a packet). Again, the Internet packet size distribution is used to adopt the more realistic scenario. The interarrival time of packets is geometrically distributed. Although the difference in the worst-case delay between VC-merging and non-VC merging can be theoretically very large, we consistently observe that the difference in average
研究小区重组对分组延迟的影响很有意义。这里我们只考虑在一个节点上的延迟；端到端延迟是正在进行的工作的主题。我们将数据包的延迟定义为数据包的第一个小区到达交换机和同一数据包的最后一个小区离开之间的时间。我们研究了在r_s=1（数据包中的背靠背单元）的情况下，VC合并和非VC合并交换机的平均数据包延迟作为利用率的函数。同样，互联网数据包大小分布用于采用更现实的场景。数据包的到达间隔时间是几何分布的。虽然VC合并和非VC合并在最坏情况下的延迟在理论上可能相差很大，但我们始终观察到平均延迟的差异
delays of the two systems to be consistently about one average packet time for a wide range of utilization. The difference is due to the average time needed to reassemble a packet.
两个系统的延迟在广泛的利用率范围内保持一致，约为一个平均数据包时间。这种差异是由于重新组装数据包所需的平均时间造成的。
To see the effect of cell spacing in a packet, we again simulate the average packet delay for r_s=0.2. We observe that the difference in average delays of VC merging and non-VC merging increases to a few packet times (approximately 20 cells at high utilization). It should be noted that when a VC-merge capable ATM switch reassembles packets, in effect it performs the task that the receiver has to do otherwise. From practical point-of-view, an increase in 20 cells translates to about 60 micro seconds at OC-3 link speed. This additional delay should be insignificant for most applications.
为了观察分组中小区间隔的影响，我们再次模拟r_s=0.2的平均分组延迟。我们观察到，VC合并和非VC合并的平均延迟差异增加到几个包的时间（在高利用率下大约20个单元）。应该注意的是，当支持VC合并的ATM交换机重新组装数据包时，实际上它执行了接收方必须执行的任务。从实际角度来看，在OC-3链路速度下，增加20个小区可转化为约60微秒。对于大多数应用程序来说，这种额外的延迟应该是微不足道的。
There are no security considerations directly related to this document since the document is concerned with the performance implications of VC merging. There are also no known security considerations as a result of the proposed modification of a legacy ATM LSR to incorporate VC merging.
由于本文档涉及VC合并的性能影响，因此没有与本文档直接相关的安全注意事项。由于建议修改传统ATM LSR以合并VC合并，因此也没有已知的安全考虑因素。
This document has investigated the impacts of VC merging on the performance of an ATM LSR. We experimented with various traffic processes to understand the detailed behavior of VC-merge capable ATM LSRs. Our main finding indicates that VC merging incurs a minimal overhead compared to non-VC merging in terms of additional buffering. Moreover, the overhead decreases as utilization increases, or as the traffic becomes more bursty. This fact has important practical consequences since switches are dimensioned for high utilization and stressful traffic conditions. We have considered the case where the output buffer uses a FIFO scheduling. However, based on our investigation on slow sources, we believe that fair queueing will not introduce a significant impact on the additional amount of buffering. Others may wish to investigate this further.
本文研究了VC合并对ATM LSR性能的影响。我们对各种业务流程进行了实验，以了解支持VC合并的ATM LSR的详细行为。我们的主要发现表明，就附加缓冲而言，与非VC合并相比，VC合并产生的开销最小。此外，开销随着利用率的增加而减少，或者随着流量变得更加突发而减少。这一事实具有重要的实际后果，因为交换机的尺寸适合高利用率和紧张的交通条件。我们考虑了输出缓冲区使用FIFO调度的情况。然而，根据我们对慢源的调查，我们相信公平排队不会对额外的缓冲量产生显著影响。其他人可能希望对此进行进一步调查。
The authors thank Debasis Mitra for his penetrating questions during the internal talks and discussions.
作者感谢Debasis Mitra在内部会谈和讨论中提出的尖锐问题。
[1] P. Newman, Tom Lyon and G. Minshall, "Flow Labelled IP: Connectionless ATM Under IP", in Proceedings of INFOCOM'96, San-Francisco, April 1996.
[1] P.Newman、Tom Lyon和G.Minshall，“流量标签IP：IP下的无连接ATM”，1996年4月，旧金山，INFOCOM'96会议录。
[2] Rekhter,Y., Davie, B., Katz, D., Rosen, E. and G. Swallow, "Cisco Systems' Tag Switching Architecture Overview", RFC 2105, February 1997.
[2] Rekhter，Y.，Davie，B.，Katz，D.，Rosen，E.和G.Swallow，“思科系统标签交换体系结构概述”，RFC 2105，1997年2月。
[3] Katsube, Y., Nagami, K. and H. Esaki, "Toshiba's Router Architecture Extensions for ATM: Overview", RFC 2098, February 1997.
[3] Katsube，Y.，Nagami，K.和H.Esaki，“东芝的ATM路由器架构扩展：概述”，RFC 2098，1997年2月。
[4] A. Viswanathan, N. Feldman, R. Boivie and R. Woundy, "ARIS: Aggregate Route-Based IP Switching", Work in Progress.
[4] A.Viswanathan、N.Feldman、R.Boivie和R.Woundy，“ARIS：基于聚合路由的IP交换”，正在进行中。
[5] R. Callon, P. Doolan, N. Feldman, A. Fredette, G. Swallow and A. Viswanathan, "A Framework for Multiprotocol Label Switching", Work in Progress.
[5] R.Callon、P.Doolan、N.Feldman、A.Fredette、G.Swallow和A.Viswanathan，“多协议标签交换框架”，正在进行中。
[6] WAN Packet Size Distribution, http://www.nlanr.net/NA/Learn/packetsizes.html.
[6] WAN数据包大小分布，http://www.nlanr.net/NA/Learn/packetsizes.html.
[7] Heinanen, J., "Multiprotocol Encapsulation over ATM Adaptation Layer 5", RFC 1483, July 1993.
[7] Heinanen，J.，“ATM适配层5上的多协议封装”，RFC 1483，1993年7月。
[8] P. Jacobs and P. Lewis, "Discrete Time Series Generated by Mixtures III: Autoregressive Processes (DAR(p))", Technical Report NPS55-78-022, Naval Postgraduate School, 1978.
[8] P.Jacobs和P.Lewis，“由混合物III生成的离散时间序列：自回归过程（DAR（P））”，技术报告NPS55-78-022，海军研究生院，1978年。
[9] B.K. Ryu and A. Elwalid, "The Importance of Long-Range Dependence of VBR Video Traffic in ATM Traffic Engineering", ACM SigComm'96, Stanford, CA, pp. 3-14, August 1996.
[9] B.K.Ryu和A.Elwalid，“ATM流量工程中VBR视频流量长距离依赖的重要性”，ACM SigComm'96，加利福尼亚州斯坦福，第3-14页，1996年8月。
Authors' Addresses
作者地址
Indra Widjaja Fujitsu Network Communications Two Blue Hill Plaza Pearl River, NY 10965, USA
Indra Widjaja Fujitsu Network Communications Two Blue Hill Plaza Pearl River，NY 10965，美国纽约州
Phone: 914 731-2244 EMail: indra.widjaja@fnc.fujitsu.com
电话：914731-2244电子邮件：indra。widjaja@fnc.fujitsu.com
Anwar Elwalid Bell Labs, Lucent Technologies 600 Mountain Ave, Rm 2C-324 Murray Hill, NJ 07974, USA
安瓦尔·埃尔瓦利德·贝尔实验室，朗讯科技公司，美国新泽西州默里山山路600号2C-324室，邮编：07974
Phone: 908 582-7589 EMail: anwar@lucent.com
电话：908582-7589电子邮件：anwar@lucent.com
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Acknowledgement
确认
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